A field effect device, in its simplest form, comprises a conductive region of semiconductive material, such as silicon, which is modulated using electric fields. Such modulation can be used in transistor devices, such as a junction field effect transistor (JFET), to obtain a voltage variable resistor. As is well known, these devices have majority carrier flow through a conducting region or channel whose cross section can be varied by the application of an external electric field. There are two general types of JFETs, those which are "normally on" (i.e. operating in a depletion mode) wherein the space charge region thickness is significantly less than the channel thickness at zero voltage, and those [and those] which are "normally off" (i.e. operating in an enhancement mode) wherein the built-in potential is such that the channel is closed at zero applied voltage.
With reference now to FIG. 1, there is shown an n-channel junction field effect transistor (JFET) 2 fabricated, in accordance with the prior art, to operate in a depletion mode. As seen in FIG. 1, the prior art JFET consists of a channel of n-type semiconductive material 3, such as silicon, having gates 4 and 5 formed by diffusing a p-type impurity on opposite surfaces thereof. Ohmic contacts 6 and 7 are made to the ends of the channel 3, these forming the source and drain, respectively. Current I.sub.s is caused to flow along the length of the channel because of the voltage supply connected between source 6 and drain 7. This current consists of majority carriers, which in the illustrative device, are electrons. As is well known in the art, a negative gate voltage creates two high resistance regions 8 and 9 in the channel adjacent to the gates 4 and 5, respectively. The conductivity of these regions is nominally zero because of the unavailability of current carriers. Hence, the effective width of the channel in FIG. 1 will decrease with increasing reverse bias. When the pinch-off voltage is reached, the channel width is reduced to zero because all of the free charge has been removed from the channel.
Efforts in the prior art to improve upon the conventional planar field effect transistor have resulted in various modifications. In FIG. 2, there is shown a V-groove FET, which utilizes a non-planar structure to provide a higher transconductance and a lower turn-on resistance than the conventional planar FET. As shown in FIG. 2, the V-groove FET is typically formed from an n-type silicon epitaxial layer 3' on a p-type substrate 5'. The device has three sets of V-shaped grooves that form the gate G, drain D, and source S, and isolation regions. Numeral 4' refers to a p+ or Schottky barrier between an ohmic contact layer of aluminum and the n-channel. Because the equivalent channel length is smaller than the gate opening L, the channel conductance is larger than a planar FET with the same device geometry. In the saturation region, the device is pinched off at a point near the middle of the channel, instead of at the drain end as in the planar FET. The equivalent channel length in the saturation region is also less than the gate opening. Consequently, the transconductance is larger than that of the conventional planar FET. A primary disadvantage of the V-groove FET, however, is that it is a complex structure which is very expensive to manufacture.
Accordingly it is an object of the present invention to provide a FET device which exhibits high transconductance and a low turn-on resistance, yet which is simple and economical to manufacture. Other advantages of the present invention regarding superior operating conditions over the v-groove FET will be discussed.